Silicon Canvas delivers Laker T1 to ASPLA as its Test Chips Platform
TOKYO, OCTOBER 27, 2003 - - - Advanced SoC Platform Corporation (ASPLA), a company established to promote the unification of design and manufacturing technologies for next-generation System-on-Chip (SoC), and Silicon Canvas, Inc. (SCI), an EDA company that provides test chip development platform and next-generation custom layout solutions, today announced that ASPLA has adopted Laker T1 as its 90 nm(nanometer) test chips development platform.
"ASPLA is indeed one of its kind in pioneering technology advancement as well as business innovation for the next era.", says Dr. Hau-Yung Chen, President at Silicon Canvas, Inc. "We are very glad to partner with ASPLA. Through Laker T1, we offer automation and correct by construction test chip layout implementation resulting in a standardized test chip platform that can be re-used at any process derivatives and future technology nodes."
ASPLA is a collaborative research organization comprising Fujitsu, Matsushita, NEC Electronics, Renesas, Toshiba, and five other companies. The ten member companies are working together to establish a design and manufacturing technology platform to drive the fabrication of semiconductor devices in 90nm and lower process technologies in Japan.
"The semiconductor business model has shifted from the conventional Integrated Device Manufacturer (IDM) model in the '80s, to the Foundry and Fabless model in the '90s, and now to the turning point where an open, System-on-Chip (SoC) platform model is imperative.", says Dr. Keiichi Kawate, President and CEO of ASPLA, "ASPLA's mission is to develop such a platform for the design and manufacture of next-generation, 90 nanometer semiconductor devices. This cooperation with Silicon Canvas will help to shorten the development time in advanced process of each member company."
About Laker T1:
Laker T1 delivers at least ten-fold productivity gain in test chip implementation through reusable, transferable and manageable architecture with centralized access control. Laker T1 provides an intuitive user interface to define parameterized test structures and test lines, which speed up technology time to market while allowing last-minute test chip specification change.
Laker T1 is available now for Unix and Linux machine.
About Silicon Canvas:
Silicon Canvas is the technology leader in providing test chip development platform and full-custom layout solutions for products and services. Founded in 2000 by Dr. Hau-Yung Chen in conjunction with other EDA veterans with combined over 50+ years of experience.
The company's custom layout tool, Laker, addresses the ever-important needs of today's analog, mixed-signals, large complex IC, ASIC, and SoC designs. Silicon Canvas' custom layout solutions provide more automation and high performance capabilities to any design projects, which require the use of more effective full-custom layout solutions, including but not limited to the layout creation for analog, mixed-signals, and test chip designs, etc. Customers' applications include processors, computing systems, networking, telecommunication and graphics.
For more information, please contact:
Silicon Canvas, Inc.
Hau-Yung Chen
2665 N. First Street
Suite 212
San Jose, CA 95134
USA
Phone: +1(408) 321-0888
FAX: +1(408) 321-0880
E-mail: hchen@sicanvas.com
